In this scenario, the launch clock
CLK1 is the slow clock; the capture clock
CLK2 is the fast clock. See the following figure.
For example, assume the following:
CLK2is three times the frequency of
- A clock enable signal on the receiving registers allows a Multicycle constraint to be set between both clocks. See the following figure.
The setup and hold relationships that are resolved by the STA tool when no multicycle is applied are shown in the following figure.