Placement constraints are applied to cells to control their locations within the device. The Vivado Integrated Design Environment (IDE) supports many of the same placement constraints as the Integrated Software Environment (ISE) Design Suite and the PlanAhead™ tool.
- A unique string name applied to two LUTs to control their placement on a single LUT site. Unlike HLUTNM, LUTNM can be used to combine LUTs that belong to different hierarchical cells.
- A unique string name applied to two LUTs in the same hierarchy to control their placement on a single LUT site. Use HLUTNM within a cell that is instantiated multiple times.
- Disallows placement to a site.
- Attached to logical blocks to constrain them to a physical region in the
device. PBLOCK is a read-only cell property that is the name of the Pblock
to which the cell is assigned. Cell Pblock membership can be changed only by
using the XDC Tcl commands
add_cells_to_pblock and remove_cells_from_pblock.
- Specifies the location of a design port on a pin of the target device package.
- Places a logical element from the netlist to a site on the device.
- Places a logical element from the netlist to a specific BEL within a slice on the device.
For more information, see: