The Timing Constraints Wizard identifies missing timing constraints on a synthesized or implemented design. It analyzes the netlist, the clock nets connectivity, and the existing timing constraints in order to provide recommendations as per the UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949). Three categories of constraints are covered by the following 11 pages of the wizard, followed by a summary. The following steps are included:
- Primary clocks
- Generated clocks
- Forwarded clocks
- External feedback delays
- Input and output ports
- Input delays
- Output delays
- Combinatorial delays
- Clock domain crossing
- Physically exclusive clock groups
- Logically exclusive clock groups with no interaction
- Logically exclusive clock groups with interaction
- Asynchronous clock domain crossings
- Constraints summary
During each step, you can accept the recommended constraints or modify the list by checking or unchecking each of the proposed constraints. However, unchecking recommended constraints early in the wizard can prevent the identification of other missing constraints in subsequent steps. For example, if you decide to skip the creation of a clock, the wizard will not identify and recommend any constraints that refer to this clock or its auto-derived clocks.
The final page of the wizard provides a summary of the constraints that will be created. You can click on each individual hyperlink to see the constraints details, or visualize the new constraints in the Timing Constraints window after exiting the wizard.
You can also choose to generate the following recommended reports upon clicking Finish to verify that the design is completely and properly constrained:
- Create Timing Summary report
- Timing slack is reported with the new constraints, in addition to a check_timing report. Timing violations will likely display if the period or I/O delay constraints that you entered are too difficult.
- Create Check Timing report
- This report identifies missing or inappropriate constraints by running the
- Create DRC Report using only Timing Checks
- This report runs the Timing DRCs.
The Timing Constraint Wizard does not recommend a constraint if it introduces
unsafe timing analysis. Also, the wizard does not fix inappropriate constraints that
already existed when loading the design in memory. Nevertheless, some invalid
constraints might become valid after creating all the missing clocks when using Vivado Design Suite in project mode; for more details, see
Constraints Processing Order and Invalid Constraints, below. Also, after using the wizard, if
report_drc still flag some
constraints issues, it is usually due to a constraint problem that already existed in
the source XDC files. You must address these problems directly instead of using the
wizard to resolve them.