Use of set_output_delay Command Options - 2022.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

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2022.1 English

The following examples present typical uses of the set_output_delay command options. For additional information about output delay constraint methodology, refer to this link in the UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949).

Output Delay Example One

This example defines an output delay relative to a previously defined sysClk for both min and max analysis.

> create_clock -name sysClk -period 10 [get_ports CLK0]
> set_output_delay -clock sysClk 6 [get_ports DOUT]

Output Delay Example Two

This example defines an output delay relative to a previously defined virtual clock.

> create_clock -name clk_port_virt -period 10
> set_output_delay -clock clk_port_virt 6 [get_ports DOUT]

Output Delay Example Three

This example specifies output delay value relative to a DDR clock with different values for min (hold) and max (setup) analysis.

> create_clock -name clk_ddr -period 6 [get_ports DDR_CLK_IN]
> set_output_delay -clock clk_ddr -max 2.1 [get_ports DDR_OUT]
> set_output_delay -clock clk_ddr -max 1.9 [get_ports DDR_OUT] -clock_fall -add_delay
> set_output_delay -clock clk_ddr -min 0.9 [get_ports DDR_OUT]
> set_output_delay -clock clk_ddr -min 1.1 [get_ports DDR_OUT] -clock_fall -add_delay

This example creates constraints from data launched by both rising and falling edges of the clk_ddr clock outside the device, to the data output of the internal flip-flop sensitive to both rising and falling clock edges.

Figure 1. Output Delay Example 3

Output Delay Example Four

This example specifies the clock and output delay on the STARTUPE3 internal pins (UltraScale+ devices) to time the paths from the fabric to STARTUPE3.

>	create_generated_clock -name clk_sck -source [get_pins -hierarchical
*axi_quad_spi_0/ext_spi_clk] [get_pins STARTUP/CCLK] -edges {3 5 7}
>	set_output_delay -clock clk_sck -max 6 [get_pins STARTUP/DATA_OUT[*]]
>	set_output_delay -clock clk_sck -min 1 [get_pins STARTUP/DATA_OUT[*]]
For more information on timing constraints for STARTUPE3, refer to the AXI Quad SPI LogiCORE IP Product Guide (PG153).