set_bus_skew Example One - 2022.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

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2022.1 English

In this example, the CDC is part of a handshake mechanism. The source clock domain generates a send signal when data is available to be sampled. The destination clock domain uses a 4-stage synchronizer for the send signal. After the 4-stage synchronizer, the signal drives the Clock Enable pin of the CDC destination registers. In such Clock-Enabled Control CDC structure, the bus skew must be adjusted to the number of stages on the CE path since it represents the number of destination clock cycles for which the data is valid.

If the source clock period is 5 ns and the destination clock period is 2.5 ns, the bus skew on the CDC path should be set to 10 ns (4×2.5 ns).

set_bus_skew -from [get_cells src_hsdata_ff_reg*] -to [get_cells dest_hsdata_ff_reg*] 10.000
Figure 1. set_bus_skew Example One

Note: For completeness, the CDC needs an additional set_max_delay constraint to ensure that the source and destination registers are not placed too far apart:
set_max_delay -datapath_only -from [get_cells src_hsdata_ff_reg*] -to [get_cells dest_hsdata_ff_reg*] 10.000