- Assembles the netlist.
The netlist is assembled from multiple sources if needed. Designs can consist of a mix of structural Verilog, EDIF, and Vivado IP.Important: NGC format files are not supported in the Vivado Design Suite for UltraScale™ devices. It is recommended that you regenerate the IP using the Vivado Design Suite IP customization tools with native output products. Alternatively, you can use the convert_ngc Tcl utility to convert NGC files to EDIF or Verilog formats. However, Xilinx recommends using native Vivado IP rather than XST-generated NGC format files going forward.
- Transforms legacy netlist primitives to the currently supported subset of Unisim
report_transformed_primitivesto generate a list of transformed cells.
- Processes constraints from XDC files.
These constraints include both timing constraints and physical constraints such as package pin assignments and Pblocks for floorplanning.Important: Review critical warnings that identify failed constraints. Constraints might be placed on design objects that have been optimized or no longer exist. The Tcl command '
write_xdc -constraints INVALID' also captures invalid XDC constraints.
- Builds placement macros.
The Vivado tools create placement macros of cells, based on their connectivity or placement constraints to simplify placement.
Examples of placement macros include:
- An XDC-based macro.
- A relatively placed macro (RPM).Note: RPMs are placed as a group rather than as individual cells.
- A long carry chain that needs to be placed in multiple CLBs.Note: The primitives making up the carry chains must belong to a single macro to ensure that downstream placement aligns it into vertical slices.
To create the in-memory design, the Vivado Design Suite uses the following process to combine the netlist files, constraint files, and the target part information: