During floorplanning, the design is partitioned into clusters of related logic and initial locations are chosen based on placement of I/O and clocking resources. Pblock constraints are treated as hard during this phase, even if they have the IS_SOFT property set to True. When targeting SSI devices, the design is also partitioned into different SLRs to minimize SLR crossings and their associated delay penalties. Soft SLR floorplan constraints can be applied to guide the logic partitioning during this phase. For more information about Using Soft SLR Floorplan Constraints, see the UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949).