The Vivado Design Suite supports netlist-driven design by importing
previously synthesized netlists from Xilinx or third-party tools.
The netlist input formats include:
- Structural Verilog
- Structural SystemVerilog
- Synthesized Design Checkpoint (DCP)
Important: NGC format files are not
supported in the Vivado Design Suite for UltraScale and later devices. It is recommended that you
regenerate the IP using the Vivado Design Suite IP
customization tools with native output products. Alternatively,
convert_ngc Tcl utility to convert NGC files to EDIF or Verilog
formats. However, Xilinx recommends using native
Vivado IP rather than XST-generated NGC format
files going forward.
When using IP in Project
Mode or Non-Project Mode, always use the XCI file and not the DCP file. This ensures
that IP output products are used consistently during all stages of the design flow. If
the IP was synthesized out-of-context and already has an associated DCP file, the DCP
file is automatically used and the IP is not re-synthesized. For more information, see
section Adding Existing IP to a Project in the
Vivado Design Suite User Guide: Designing with
For more information on the source files and project types supported by the Vivado Design Suite, see the
Vivado Design Suite User Guide:
System-Level Design Entry (UG895).