The Vivado tools build an in-memory
view of the design using
link_design command combines the netlist based source files
read into the tools with the Xilinx part
information, to create a design database in memory.
There are two important
-partoption specifies the target device.
-topoption specifies the top design for implementation. If the top-level netlist is EDIF and the
-topoption is not specified, the Vivado tools will use the top design embedded in the EDIF netlist. If the top-level netlist is not EDIF but structural Verilog, the -top option is required. The -top option can also be used to specify a submodule as the top, for example when running the Module Analysis flow to estimate performance and utilization.
All actions taken in Non-Project Mode are directed at the in-memory database within the Vivado tools.
The in-memory design resides in the Vivado IDE for interaction with the design data in a graphical form. tools, whether running in batch mode, Tcl shell mode for interactive Tcl commands, or in the