Use Case 3: Adding a Pipeline Stage to Improve Timing - 2022.1 English

Vivado Design Suite User Guide: Implementation (UG904)

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2022.1 English

Adding registers along a path to split combinational logic into multiple cycles is called pipelining. Pipelining improves register-to-register performance by introducing additional latency in the pipelined path. Whether pipelining works depends on the latency tolerance of your design. The schematic in the following figure shows the critical path originating at a RAMB36E1 and going through two LUT6 cells before terminating at an FF. Adding a pipeline stage can improve timing for the critical path and can be accomplished by modifying the netlist.

Figure 1. Schematic Prior to Addition of Pipeline Register

The following Tcl script shows how to insert a pipeline register between the two LUT6 cells. The register is implemented with the same control signals as the load register.

create_cell -reference [get_lib_cells -of [get_cells {wbOutputData_reg[29]}]] ECO_pipe_stage[29]
foreach control_pin {C CE R} {
connect_net -net [get_nets -of [get_pins wbOutputData_reg[29]/${control_pin}]] \
-objects [get_pins ECO_pipe_stage[29]/${control_pin}]
disconnect_net -objects \
{egressLoop[4].egressFifo/buffer_fifo/infer_fifo.block_ram_performance.fifo_ram_reg/DOBDO[ 29]}
create_net {egressLoop[4].egressFifo/buffer_fifo/ECO_pipe_stage[29]_in} connect_net -hierarchical -net
{egressLoop[4].egressFifo/buffer_fifo/ECO_pipe_stage[29]_in} -objects \ [list \
{ECO_pipe_stage[29]/D} \

{egressLoop[4].egressFifo/buffer_fifo/infer_fifo.block_ram_performance.fifo_ram_reg/DOBDO[ 29]}]
connect_net -hierarchical -net {egressLoop[4].egressFifo/buffer_fifo/dout2_in[29]}
-objects [list \ {ECO_pipe_stage[29]/Q}]

The following figure shows the schematic of the resulting logical netlist changes.

Figure 2. Schematic Showing Addition of Pipeline Register

After the netlist has been successfully modified, the logical changes must be committed. Accomplish this using the place_design and route_design commands.