Using Auto-Pipelining on Custom Interfaces - 2022.1 English

Vivado Design Suite User Guide: Implementation (UG904)

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2022.1 English

Auto-pipelining is not limited to the AXI Register Slice IP. You can also control auto-pipelining on custom interfaces using the properties shown in the following table, which are specified in the RTL. For more information, see the Vivado Design Suite Properties Reference Guide (UG912).

Table 1. Properties for Auto-Pipelining on Custom Interfaces
Property Name Object Format/Range Description
AUTOPIPELINE_MODULE hierarchical cell Boolean Establishes a separate name-space for all group names defined throughout sub-hierarchies. This property must be used when a module with auto-pipelining properties is instantiated several times in the design.
AUTOPIPELINE_GROUP net String (case-insensitive) Establishes the auto-pipeline group name of signals that must receive an equal number of auto-inserted pipeline flip-flops.
AUTOPIPELINE_INCLUDE net String (case-insensitive) Specifies the name of another AUTOPIPELINE_GROUP to include when applying the AUTOPIPELINE_LIMIT.
AUTOPIPELINE_LIMIT net 0 < integer <= 24 Defines the maximum number of auto-inserted pipeline flip-flops for associated groups.

All nets that belong to the same AUTOPIPELINE_GROUP must have an equal number of pipeline registers inserted on each tagged signal. Following are additional considerations:

  • If an AUTOPIPELINE_GROUP does not reference an AUTOPIPELINE_INCLUDE group, the number of pipeline stages inserted into the AUTOPIPELINE_GROUP must be between 0 and the AUTOPIPELINE_LIMIT.
  • If an AUTOPIPELINE_GROUP references an AUTOPIPELINE_INCLUDE group, the sum of the pipeline stages inserted into the AUTOPIPELINE_GROUP and the AUTOPIPELINE_INCLUDE group must be between 0 and the AUTOPIPELINE_LIMIT.

When you specify the AUTOPIPELINE_GROUP, AUTOPIPELINE_LIMIT, and AUTOPIPELINE_INCLUDE properties on a register in RTL, the Vivado tools automatically propagate the properties to the net directly connected to the output of the register. For best timing QoR, Xilinx recommends the following:

  • Only apply the AUTOPIPELINE_* properties to registers with no clock enable and no reset control signals.
  • Create distinct hierarchies for both sides of the interface, and apply a different USER_SLR_ASSIGNMENT with a different string to each side. The strings must not be SLR<n>. The soft floorplanning constraints guide the Vivado placer to move the two groups of registers to different SLRs as needed to improve timing QoR. For example, if hierarchy hierA includes the source registers, and hierB includes the destination registers, you must add the following constraints:
    set_property USER_SLR_ASSIGNMENT apSrcGrpA [get_cells hierA] 
    set_property USER_SLR_ASSIGNMENT apDstGrpB [get_cells hierB]
Important: The auto-pipelining feature changes the latency of the design. Therefore, you must ensure the functionality remains correct for the specified AUTOPIPELINE_LIMIT range. If the handshake circuitry is required, you must add appropriate logic, such as a FIFO, with enough depth to support backpressure without losing data. The Vivado tools do not verify the correctness of the design logic.
Note: For the best timing QoR results, the auto-pipeline properties must be set on registers without clock enable or reset logic.

The following figure shows how the auto-pipeline properties are used in the AXI Register Slice RTL.

Figure 1. Example of Auto-Pipelining RTL Property Usage

The following logic diagram shows one AXI channel of the AXI Register Slice with nets tagged with auto-pipeline properties.

Figure 2. Auto-Pipelining Logic Diagram