Analyzing Utilization Statistics - 2022.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2022-05-04
Version
2022.1 English

A common cause of implementation issues is not considering the explicit and implicit physical constraints. The pinout, for example, becomes an explicit physical constraint on logic placement. Slice logic is uniform in most devices. The following specialized resources, however, represent implicit physical constraints because they are only available in certain locations, and impact logic placement:

  • I/Os
  • Gigabit transceivers
  • DSP slices
  • Block RAM
  • Clock management blocks such as MMCM
  • Clock buffers such as BUFG

Blocks that are large consumers of these specialized resources might have to be spread around the device, physically constraining placement and routing when designing the interface with the rest of the design. Additionally, Pblocks are explicit physical constraints used to define allowable placement areas for specified logic. Use a combination of the following methods to analyze block resource usage on the device:

  • Report utilization
  • Netlist properties
  • Pblock properties