In the CE-controlled CDC example shown in the following figure, the clock enable signal is synchronized in the destination
clk_b domain before being used to control the crossing flip-flops.
The CDC engine only checks that the signal connected to FF3/CE is also launched by
clk_b. There is no restriction on how the clock
enable signal is synchronized
on the circuitry driving the CE pin, as long as it is separately
reported as a safe CDC path. Also, you are responsible for constraining the latency from
clk_a domain to FF3, which is usually done by a
set_max_delay -datapath_only constraint.