- LUT Combining: Combined LUT Pairs indicates that there are combined LUT pairs present in the path. While combining LUT pairs can reduce logic utilization, it can also restrict the placement solutions and can create congestion due to high pin density. If LUT combining appears to be an issue in the design, it is recommended to disable LUT combining in synthesis by using the
- Optimization Blocking: Mark Debug and Dont Touch can quickly identify whether there are any nets or cells in the path that the tool is not allowed optimize.
- The default behavior of setting the
MARK_DEBUG property is to also to set the
DONT_TOUCH property. Consider setting
FALSE to allow for optimization.
DONT_TOUCH disables optimizations such as cell or net replication. Evaluate the need for
DONT_TOUCH constraints and remove them if possible. When a net enters a hierarchical cell with
DONT_TOUCH, the portion of the net inside the hierarchical cell cannot be replicated. If
DONT_TOUCH is used to prevent logic trimming, check the design for correctness. One simple example would be logic removed due to unconnected outputs.
- Fixed Placement and Routing: The Fixed Loc, Fixed Route can quickly identify whether there are any fixed placement or fixed routing constraints that might be impacting the timing path slack.
- Using cell location constraints can help stabilizing QoR for a difficult design. If timing can no longer be met after modifying the design, you can try removing the placement constraints to give more flexibility to the placer.
- Having fixed routes prevents the router from optimizing the net delays to meet timing. A timing path with locked routing usually shares nets with other paths that can be negatively impacted by this constraint. Use fixed routes only when necessary and when it does not affect interacting paths. Always be aware that changes to other physical constraints such as Pblocks might require the fixed cell locations or fixed routes to also be updated.