You can select the interconnect model to be used in your analysis of timing paths:
- This model provides the most accurate delays for a routed design.
- This model includes an estimate of the interconnect delays based on the placement and connectivity of the design onto the device prior to implementation. Estimated delay can be specified even if the design is fully routed.
- No interconnect delay in the timing analysis is included. Only the logic delay is applied. This can help identify paths where the logic delay exceeds or takes up a significant percentage of the timing path requirement.
Equivalent Tcl command:
set_delay_model -interconnect <arg>
For more information about
refer to the
Design Suite Tcl Command Reference Guide (UG835).