Timing Path Characteristics Report - 2022.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2022-05-04
Version
2022.1 English

The following figure shows example output after running the Report Design Analysis in Timing Mode to show the path characteristics of only the ten worst setup paths in the design. Generate the report from the Vivado IDE by selecting Reports > Report Design Analysis, or use the following Tcl command:

report_design_analysis -name <arg>
Tip: To create hold path characteristics, select Path delay type: min in the Options tab of the Report Design Analysis dialog box or add -hold to the Tcl command. For more information on Tcl command syntax, see the Vivado Design Suite Tcl Command Reference Guide (UG835) .
Figure 1. Example Setup Path Characteristics

Report Design Analysis can also provide a Logic Level Distribution table for the worst timing paths. The default number of paths analyzed for the Logic Level Distribution table is 1,000 and can be changed in the Report Design Analysis dialog box. The Logic Level Distribution table is not generated by default but can be generated when you select Include logic level distribution in the Report Design Analysis dialog box Options tab. An example of the Logic Level Distribution table is shown in the following figure.

Figure 2. Example of Logic Level Distribution Report

The logic level distribution GUI has been enhanced to include hyperlinks for the individual bins. By clicking on these hyperlinks, you can run report_design_analysis or report_timing on paths or select timing path objects as shown in the following figure.

Figure 3. Report Design Analysis on a Selected Path

The command line option -routes can be used with -logic_level_distribution to generate a report based on the number of routes instead of the number of logic levels.

Figure 4. Example of Logic Level Distribution Report with -routes

The command line options -min_level and -max_level can be used with -logic_level_distribution to control the bins.

All the paths with logic levels less than -min_level are placed in a single bin, and all the paths with logic levels greater than -max_level are placed in a single bin.

Create an individual bin for each logic level where at least one path exists in between the levels. For example, if a design has paths with logic levels of 0, 1, 3, 4, 5, 11, 12, 14, 15, 16 (see Timing Path Characteristics Report) using -min_level 3 and -max_level 11, report_design_analysis reports using the 0-2, 3, 4, 5, 11, 12+ bins.

Figure 5. Example of Logic Level Distribution Report with -min_level and -max_level