The Netlist Window shows the design hierarchy as it is in the netlist, processed by the synthesis tools. It is useful for exploring the logical hierarchy of the design.
Depending on synthesis settings, the netlist hierarchy may be a one hundred percent match for the original RTL, or there may be no hierarchy. Generally, the synthesis defaults to preserving most of the user hierarchy while optimizing the logic. This results in a smaller and faster netlist.
With the synthesis tool defaults, the netlist hierarchy is recognizable, but the interfaces to the hierarchies may be modified. Some pins and levels of hierarchy may be missing.
The netlist hierarchy is represented as a folder tree. At each level, the tool shows:
- A Nets folder for any nets at that level
- A Leaf Cells folder if there are hardware primitive instances at that level
- A hierarchy folder for any hierarchies instantiated at that level
Expanding a hierarchy folder reveals the Nets, Leaf Cells, and hierarchies at that level. The icons next to the cells display information about the state of the design.
The Cell Properties Window for the selected hierarchy provides useful information filtered by the category buttons at the bottom of the window. Selecting the Statistics button shows utilization statistics including:
- Primitive usage for the whole hierarchical branch, grouped in higher level buckets
- The number of nets crossing the hierarchy boundary
- Each clock, whether it is on global routing and the number of its loads in the current hierarchical branch
If you floorplan the design, similar properties are displayed for the Pblock.