Design clocks are the main component for dynamic power computation. If
no clocks are defined, switching activity estimates will be inaccurate, resulting in
inaccurate power estimates. A clock node is identified from timing constraints which
are defined using create_clock or create_generated_clock XDC commands.
Note: All the required
clocks in the design must be defined using
create_clock or create_generated_clock commands.The Switching tab of the Report Power dialog box displays all the clocks defined in the design.
Figure 1. Constrained Clocks for Report Power
Make sure all the clocks defined in the design are displayed. Once Report Power runs, the Power Report confirms the percentage of clocks defined in the design when you view the Confidence Level details from the Summary page. This guides you to make sure there is a HIGH confidence level on Clock Activity.
Figure 2. Confidence Level and Specified Clocks
In Tcl mode, use the
get_clocks and report_clocks
commands to get the list of defined clocks. The text report gives the Confidence
Level on Clock Activity:report_power -file power.rptFigure 3. Text Report - Confidence Level for Clock Activity
