Configuration Time - 2022.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2022-06-07
Version
2022.1 English

The speed of configuration is directly related to the size of the partial BIT file and the bandwidth of the configuration port. The different configuration ports in each device family have the maximum bandwidths shown in the followingTable 1,Table 1, and Table 2.

Table 1. Maximum Bandwidths for Configuration Ports in 7 Series Devices
Configuration Mode Max Clock Rate Data Width Maximum Bandwidth
ICAP 100 MHz 32 bit 3.2 Gb/s
SelectMAP 100 MHz 32 bit 3.2 Gb/s
Serial Mode 100 MHz 1 bit 100 Mb/s
JTAG 66 MHz 1 bit 66 Mb/s
Table 2. Maximum Bandwidths for Configuration Ports in UltraScale Devices
Configuration Mode Max Clock Rate Data Width Maximum Bandwidth
ICAP/MCAP 200 MHz 32-bit 6.4 Gb/s
ICAP/MCAP (SSI) 1 125 MHz 32-bit 4.0 Gb/s
SelectMAP 125 MHz 32 bit 4.0 Gb/s
Serial Mode 150 MHz 1 bit 150 Mb/s
Serial (SSI Devices) 100 MHz 1 bit 100 Mb/s
JTAG 50 MHz 1 bit 50 Mb/s
JTAG (SSI Devices) 20 MHz 1 bit 20 Mb/s
  1. When delivered to the master SLR to program any SLR; when programming to the same SLR as the ICAP, the faster rate can be used. Note that configuration clock frequency maximums may be less than these values depending on speed grade or operating voltage. Consult the Data Sheet for your target device for more information.
Table 3. Maximum Bandwidths for Configuration Ports in UltraScale+ Devices
Configuration Mode Max Clock Rate Data Width Maximum Bandwidth
ICAP/MCAP 200 MHz 32-bit 6.4 Gb/s
ICAP/MCAP (SSI) 1 125 MHz 32-bit 4.0 Gb/s
BPI 125 MHz 16-bit 2.0 Gb/s
QSPI 125 MHz 4-bit 500 Mb/s
SelectMAP 125 MHz 32-bit 4.0 Gb/s
Serial Mode 125 MHz 1-bit 125 Mb/s
JTAG 66 MHz 1-bit 66 Mb/s
JTAG (SSI Devices) 20 MHz 1-bit 20 Mb/s
  1. When delivered to the master SLR to program any SLR; when programming to the same SLR as the ICAP, the faster rate can be used. Note that configuration clock frequency maximums may be less than these values depending on speed grade or operating voltage. Consult the Data Sheet for your target device for more information.

In addition to being reported by write_bitstream, The exact bitstream length is available in the created.rbt file by using the -raw_bitfile option for write_bitstream. Use this number along with the bandwidth to calculate the total configuration time. Here is an example of the header in a raw bit file:

Xilinx ASCII Bitstream
Created by Bitstream 2019.2
Design name: led_shift_count;UserID=0XFFFFFFFF
Architecture: kintex7
Part:     7k325tffg900
Date:     Mon Mar 16 16:42:05 2015
Bits:     1211072
11111111111111111111111111111111