Design Revision Checks - 2022.1 English

A partial bitstream contains programming information and little else, as described in Configuring the Device. While you do not need to identify the target location of the bitstream (the die location is determined by the addressing that is part of the BIT file), there are no checks in the hardware to ensure the partial bitstream is compatible with the currently operating design. Loading a partial bitstream into a static design that was not implemented with that RM revision can lead to unpredictable behavior.

Xilinx suggests that you prefix a partial bitstream with a unique identifier indicating the particular design, revision and module that follows. This identifier can be interpreted by your configuration controller to verify that the partial bitstream is compatible with the resident design. A mismatch can be detected, and the incompatible bitstream can be rejected, before being loaded into configuration memory. This functionality must be part of your design, and would be similar to or in conjunction with decryption and/or CRC checks, as described in PRC/EPRC: Data Integrity and Security Controller for Partial Reconfiguration Application Note (v1.0) (XAPP887 ).

A bitstream feature provides a simple mechanism for tagging a design revision. The BITSTREAM.CONFIG.USR_ACCESS property allows you to enter a revision ID directly into the bitstream. This ID is placed in the USR_ACCESS register, accessible from the FPGA programmable logic through a library primitive of the same name. Partial Reconfiguration designs can read this value and compare it to information a user can add to a header of a partial bitstream to confirm the revisions of the design match. More information on this switch can be found in the application note Bitstream Identification with USR_ACCESS using the Vivado Design Suite (XAPP1232).