This section describes the implementation flow using the example from Design Structure. The first design pass contains logic for Top and module A, but information about submodules W and X is not needed at this point. The goal of the first run is to establish the implementation result for Top, down to the partition pin interfaces to RP A. The results for module A may even be discarded, but A should be a representative module to help achieve the highest quality results for Top. In the following figure, the design is completely routed and A is defined as a RP. This is a standard DFX configuration at this point.
Three key details are shown in the above figure, which represents the design state after pr_subdivide, and after netlists and constraints have been added for W and X:
- Top is implemented and locked.
- A1 is not yet implemented, and no longer defined as an RP.
- W and X are not yet implemented and are defined as RPs.