NoC Clock Gating Issue - 2022.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID

UG909

Release Date

2022-06-07

Version

2022.1 English

Versal devices have a clock gating capability within the NoC to reduce power consumption due to unused clock buffers. This feature is not supported for certain DFX use cases.

For DFX designs that contain two or more RP, this feature is automatically disabled.
For DFX designs that contain a single RP and target the VC1902 and VM1802, the feature is supported and it is ON by default.
For DFX designs that contain a single RP and target the VP1202 or VP1802, the NoC Clock Gating feature must be disabled by the user. Execute the following procedure to disable the feature:
```
set_param noc.enableNOCClockGating 0
```
Disabling this feature allows the partial PDI to function properly, but the ungated clock buffers consumes 37 mW per buffer and this additional power needs to be accounted for in Vcc_SoC rail and power supply design.