Reduce the Number of Partition Pins - 2022.1 English

In a DFX design, signals between the reconfigurable module (RM) and static region are called boundary signals. All RM pins must have a partition pin location (PPLOC) deposited on the boundary signal by the placer. The only exceptions are dedicated paths between hard primitives. The partition pin is the physical interface on fabric that separates the static and reconfigurable portions of a boundary signal.

The presence of partition pins reduces the solution space for the router, because the corresponding boundary net is always forced to route through the partition pin. To alleviate this issue, the DFX flow includes expanded routing. Expanded routing is the additional routing footprint for a reconfigurable partition (RP) that can include routing tiles from the static region.

The boundary nets of an RM have fanout in the static region as well as within the RM. In a DFX design, the loads of a boundary net in the static region are static boundary leaf cells. When a static boundary leaf cell is placed in the expanded routing footprint of an RP, the PPLOC is not needed and the router will have more flexibility routing to the static cell in subsequent RM implementations. Xilinx recommends using the expanded routing feature to reduce the dependency of the router on PPLOCs. This feature is on by default.

If PPLOC reduction is triggered for a boundary signal when a blackbox is created for the RM after initial implementation, the boundary net is removed up to the SITE or BEL pin of the static boundary leaf pin. Subsequent RM implementations route the boundary signal from the static boundary leaf pin to the RM logic. The following figure shows the PPLOC reduction in a boundary signal. LUT1 is the boundary static leaf cell and L_Y0_X is the RM.

Figure 1. Schematic of a Boundary Signal

The following figure shows the Device window for the boundary net after route_design. The boundary signal is shown in yellow, and the boundary static leaf cell is shown in magenta. In this example, the boundary static leaf cell is placed in the expanded routing footprint of an RM. After initial implementation is complete and a blackbox is created for the RM, the boundary net is removed up to the static boundary leaf pin.

Figure 2. Routed Device Window for Boundary Net

If PPLOC reduction is not triggered for a boundary signal when the blackbox is created for the RM after initial implementation, the static boundary net segment is preserved from the static leaf pin to the PPLOC. During subsequent RM implementations, boundary nets are routed only from the PPLOC to the RM logic. This reduces the solution space for the router due to the following:

• The static segment of the boundary net (from the static boundary leaf pin to the PPLOC) is locked down during all subsequent implementations. The router must obey the IS_FIXED_ROUTE constraint on the static segment of the boundary signal and cannot reroute during subsequent RM implementations.
• The presence of locked static nets (IS_FIXED_ROUTE TRUE) at the boundary of the reconfigurable Pblock causes the tool to exclude some sites from placement, because access to these sites might be blocked by the locked static nets.
• The PPLOC deposit occurs only on single or double interconnect nodes. This approach has lower connectivity than using site pins and is equivalent to having no PPLOCs.

The following figure shows the Device window for the static boundary net segment that terminates at the PPLOC when the static boundary leaf cell is not placed in the expanded routing footprint.

Figure 3. Device Window for Static Boundary Net Segment

The routing footprint of the reconfigurable Pblock (pblock_dynamic_region) is the same as the reconfigurable Pblock size (CLOCKREGION_X0Y4: CLOCKREGION_X4Y10). All of the static region logic is assigned to the static Pblock region (pblock_static_region), which is outside the routing footprint of the reconfigurable Pblock. Therefore, PPLOC reduction is not triggered, and the reconfigurable Pblock contains a large number of PPLOCs after route_design.

In the following example, static boundary leaf cells to the reconfigurable Pblock (pblock_dynamic_region) are assigned to a thin static Pblock (pblock_ii_blp_ulp_pipe_0), which is defined in the expanded routing footprint of the RP Pblock. There are no PPLOCs remaining after route_design.

The following figure shows the static boundary leaf cells assigned to a thin static Pblock defined in the expanded routing footprint of the RP.

Figure 4. Static Boundary Leaf Cells in the Expanded Routing Footprint of the RP

To achieve maximum PPLOC reduction, Xilinx recommends that you guide the placer to keep static boundary leaf cells in the expanded routing footprint of the reconfigurable Pblock. One way to achieve this is to use thin static Pblocks defined in the expanded routing footprint of the reconfigurable Pblock.