- Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)
- Dynamic Function eXchange Controller IP LogiCORE IP Product Guide (PG374)
- Dynamic Function eXchange Decoupler IP LogiCORE IP Product Guide (PG375)
- Dynamic Function eXchange Bitstream Monitor IP LogiCORE IP Product Guide (PG376)
- Dynamic Function eXchange AXI Shutdown Manager IP LogiCORE IP Product Guide (PG377)
- Demonstration of Soft Error Mitigation IP and Partial Reconfiguration Capability on Monolithic Devices (XAPP1261)
- Bitstream Loading across the PCI Express Link in UltraScale Devices for Tandem PCIe and Partial Reconfiguration (AR# 64761)
- Partial Reconfiguration of a Hardware Accelerator with Vivado Design Suite for Zynq-7000 AP SoC Processor (XAPP1231)
- Fast Partial Reconfiguration Over PCI Express Application Note (XAPP1338)
- 7 Series FPGAs Configuration User Guide (UG470)
- UltraScale Architecture Configuration User Guide (UG570)
- Zynq-7000 SoC Technical Reference Manual (UG585)
- Partial Reconfiguration User Guide (v14.5) (UG702) - For ISE Design Tools
- UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)
- 7 Series FPGAs Integrated Block for PCI Express LogiCORE IP Product Guide (PG054)
- Virtex-7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023)
- UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)
- Vivado Design Suite Tcl Command Reference Guide (UG835)
- Vivado Design Suite User Guide: Synthesis (UG901)
- Vivado Design Suite User Guide: Using Constraints (UG903)
- Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
- 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
- 7 Series FPGAs GTP Transceivers User Guide (UG482)
- MMCM and PLL Dynamic Reconfiguration Application Note (v1.8) (XAPP888)
- UltraScale Architecture Clocking Resources User Guide (UG572)
- UltraScale Architecture GTH Transceivers User Guide (UG576)
- UltraScale Architecture GTY Transceivers User Guide (UG578)
- Vivado Design Suite User Guide: Programming and Debugging (UG908)
- AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)
- Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)
- DMA/Bridge Subsystem for PCI Express Product Guide (PG195)
- UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213)
- Zynq UltraScale+ Device Technical Reference Manual (UG1085)
- Zynq UltraScale+ Device Register Reference (UG1087)
- Bitstream Identification with USR_ACCESS using the Vivado Design Suite (XAPP1232)
- Local Partial Reconfiguration Using Embedded Processing for 3D ICs (XAPP1099)
- Design Advisory for Techniques on Properly Synchronizing Flip-Flops and SRLs (AR# 44174)