BD_PIN - 2022.1 English

Vivado Design Suite Properties Reference Guide

Document ID
UG912
Release Date
2022-06-08
Version
2022.1 English

BD_PIN

Description

A block design pin, or a bd_pin object, is a point of logical connectivity on a block design cell. A block design pin allows the internal logic of a cell to be abstracted away and simplified for ease-of-use. Pins can be scalar or bus pins, and can appear on hierarchical block design cells, or leaf-level cells.

Related Objects

Figure 2-8:      Block Design Pins

X-Ref Target - Figure 2-8

X14851-block-design-pins.jpg

 

As seen in Figure 2-8, a block design pin is attached to a block design cell (bd_cell), and can be connected to other pins or ports by a net (bd_net) in the block design, or diagram.

You can query the bd_pins of bd_cell and bd_net objects:

get_bd_pins -of_objects [get_bd_cells clk_wiz_1]

In addition, you can query the bd_cell, or the bd_net, of a specific bd_pin:

get_bd_cells -of [get_bd_pins */Reset]

Properties

The specific properties on a block design pin object can vary depending on the type of the pin. The following table lists some of the properties assigned to a CLK type bd_pin object in the Vivado Design Suite, with example values:

Property        Type    Read-only  Visible  Value

CLASS           string  true       true     bd_pin

DEFAULT_DRIVER  string  true       true     0000

DIR             string  true       true     O

INTF            string  true       true     TRUE

LEFT            string  true       true     3

LOCATION        string  false      true     

NAME            string  false      true     gpio_io_o

PATH            string  true       true     /axi_gpio_0/gpio_io_o

RIGHT           string  true       true     0

TYPE            string  true       true     undef

To report the properties for the bd_net object, you can copy and paste the following command into the Vivado Design Suite Tcl shell or Tcl Console:

report_property -all [lindex [get_bd_pins */*] 0]