The CLOCK_DELAY_GROUP property identifies related clocks that have the same MMCM, PLL, GT source, or common driver that should be balanced during placement and routing to reduce clock skew on timing paths between the clocks.
TIP: Clock matching (via the CLOCK_DELAY_GROUP property) is intended for use with clocks from the same MMCM, PLL, or GT source.
Architecture Support
UltraScale, UltraScale+, and Versal ACAP architectures.
Applicable Objects
•Clock net segments (get_nets) directly connected to the output of global clock buffers (BUFG, BUFGCE, BUFGMUX, BUFGCTRL, BUFGCE_DIV, BUFG_GT) that need to be balanced.
Values
•<name>: A unique string identifier used by the Vivado placer to match the delays on specified clock nets.
Syntax
Verilog and VHDL Syntax
Not applicable
XDC Syntax
set_property CLOCK_DELAY_GROUP <name> [get_nets <clk_nets>]
set_property CLOCK_DELAY_GROUP <name> [get_nets -of_objects [get_pins <clock_buffer>/O]
Where
•<name> is the unique name to associate with the specified clock nets.
•<clk_nets> is a list of clock nets directly connected to the output of global clock buffers, that are driven by a common cell, such as an MMCM for example.
XDC Syntax Example
# Define a clock group to reduce skew between the nets.
set_property CLOCK_DELAY_GROUP grp12 [get_nets {clk1_net clk2_net}]
Affected Steps
•Place Design
•report_drc
See Also