Xilinx devices support configuration interfaces with 3.3V, 2.5V, 1.8V, or 1.5V I/O. The configuration interfaces include the JTAG pins in bank 0, the dedicated configuration pins in bank 0, and the pins related to specific configuration modes in bank 14 and bank 15 in the 7 series devices, and bank 65 in the UltraScale architecture. You can set the CONFIG_VOLTAGE property, or VCCO_0 voltage, to 3.3, 2.5, 1.8, or 1.5.
CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. Refer to the 7 Series FPGAs Configuration User Guide (UG470) [Ref 1], or the UltraScale Architecture Configuration User Guide (UG570) [Ref 7] for more information on configuration voltage.
The CFGBVS pin setting determines the I/O voltage support for bank 0 at all times. For 7 series devices in which bank 14 and bank 15 are the HR bank type, or bank 65 in UltraScale architecture, the CFGBVS pin and the respective CONFIG_VOLTAGE property determine the I/O voltage support during configuration.
Report DRC checks are run on Bank 0, 14, and 15 in the 7 series, or 0 and 65 in the UltraScale architecture, to determine compatibility of CONFIG_MODE settings on the current design. DRCs are issued based on IOSTANDARD and CONFIG_VOLTAGE settings for the bank. The configuration voltages are also used when exporting IBIS models.
Architecture Support
All architectures.
Applicable Objects
•Designs (current_design)
Values
•1.5, 1.8, 2.5, or 3.3
IMPORTANT: For UltraScale+ devices, the CONFIG_VOLTAGE value must be 1.8.
Syntax
Verilog and VHDL Syntax
Not applicable
XDC Syntax
set_property CONFIG_VOLTAGE {1.5 | 1.8 | 2.5 | 3.3} [current_design]
XDC Syntax Example
# Configure I/O Bank 0 for 1.8V operation
set_property CONFIG_VOLTAGE 1.8 [current_design]
Affected Steps
•Place Design
•report_drc
•Write Bitstream
See Also