The advanced differential termination (DIFF_TERM_ADV) property is intended for use with UltraScale architecture only, and is used to enable or disable the built-in, 100W, differential termination for inputs or bidirectional ports. DIFF_TERM_ADV indicates a differential termination method should be used on differential input and bidirectional port buffers, and that the Vivado Design Suite should add on-chip termination to the port.
DIFF_TERM_ADV is only available for inputs and bidirectional ports and can only be used with the appropriate VCCO voltage. The VCCO of the I/O bank must be connected to 1.8V for HP I/O banks, and 2.5V for HR I/O banks to provide 100W of effective differential termination. Refer to the UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 8] for more information.
IMPORTANT: To support the migration of 7 Series designs to UltraScale architecture, the Vivado tool. will automatically migrate the DIFF_TERM property to the DIFF_TERM_ADV property. However, in some cases this property is not supported, and should not be specified, or should be specified as “” (NULL) value.
Architecture Support
UltraScale devices.
Applicable Objects
•Ports (get_ports)
°Input or bidirectional ports connected to a differential input buffer
•Applicable to objects using one of the following IOSTANDARDs:
°LVDS, LVDS_25, MINI_LVDS_25, SUB_LVDS
°PPDS_25
°RSDS_25
°SLVS_400_25, and SLVS_400_18
Value
•TERM_100: Utilize the 100W on-chip differential termination.
•TERM_NONE: Do not utilize the on-chip differential termination (default).
Note: The TERM_NONE value is the default value when the DIFF_TERM_ADV property is valid, such as for supported IOSTANDARDs and voltage levels. However, where it is not supported, it should not be specified and DIFF_TERM_ADV=TERM_NONE can result in a DRC violation. In these cases you can set the property to a NULL value using one of the following commands:
reset_proeprty DIFF_TERM_ADV [get_ports <port_name>]
-or-
set_property DIFF_TERM_ADV "" [get_ports <port_name>]
Syntax
Verilog and VHDL Syntax
Not applicable
XDC Syntax
set_property DIFF_TERM_ADV TERM_100 [get_ports <port_name>]
Where:
•set_property DIFF_TERM_ADV can be assigned to input or bidirectional ports.
•port_name is an input or bidirectional port connected to a differential buffer.
XDC Syntax Example
# Enables differential termination on port named CLK_p
set_property DIFF_TERM_ADV TERM_100 [get_ports CLK_p]
Affected Steps
•I/O Planning
•report_drc
•report_ssn
•report_power
See Also