DONT_TOUCH directs the tool to not optimize a user hierarchy, instantiated component, or signal, so that optimization does not occur across the module boundary, or eliminate the object. While this can assist floorplanning, analysis, and debugging, it can inhibit optimization, resulting in a larger, slower design.
IMPORTANT: Xilinx recommends setting this attribute in the RTL source files. Signals that need to be kept are often optimized before the XDC file is read. Therefore, setting this attribute in the RTL ensures that the attribute is used.
The DONT_TOUCH property works in the same way as KEEP or KEEP_HIERARCHY; however, unlike KEEP and KEEP_HIERARCHY, DONT_TOUCH is forward-annotated to place and route to prevent logic optimization during implementation. The effect of DONT_TOUCH on various objects is as follows:
•Primitive Instance: Do not remove the instance. However, the tool can connect or disconnect pins of the instance.
•Hierarchical Instance: Do not remove the instance or add or remove any pins of the instance. The tool can connect or disconnect pins and optimize logic inside the hiearchical module. However, optimization can not move logic into or out of the hierarchical module. This is a constraint on the hierarchical boundary of the instance.
TIP: Register all the outputs of a hierarchical instance with DONT_TOUCH applied.
•Hierarchical Net: Do not remove the net, or connect or disconnect any pins on the net.
TIP: On a hierarchical net, DONT_TOUCH will preserve only the hierarchical segment it is attached to, so you will need to attach it to all segments you want to preserve.
DONT_TOUCH is not supported on in individual ports of a module or entity. If you need to preserve specific ports put DONT_TOUCH on the module itself, or use the following Vivado synthesis setting:
flatten_hierarchy = “none”
Be careful when using DONT_TOUCH, KEEP, or KEEP_HIERARCHY. In cases where other attributes are in conflict with DONT_TOUCH, the DONT_TOUCH attribute takes precedence.
Architecture Support
All architectures.
Applicable Objects
•This attribute can be placed on any signal, hierarchical module, or primitive instance.
°Cells (get_cells)
°Nets (get_nets)
Values
•FALSE: Allows optimization across the hierarchy. This is the default setting.
•TRUE: Preserves the hierarchy by not allowing optimization across the hierarchy boundary. Preserves an instantiated component or a net to prevent it from being optimized out of the design.
Syntax
Verilog Syntax
Place the Verilog attribute immediately before the user hierarchy instantiation:
(* DONT_TOUCH = "{TRUE|FALSE}" *)
Verilog Syntax Example
// Preserve the hierarchy of instance CLK1_rst_sync
(* DONT_TOUCH = "TRUE" *) reset_sync #(
.STAGES(5)
) CLK1_rst_sync (
.RST_IN(RST | ~LOCKED),
.CLK(clk1_100mhz),
.RST_OUT(rst_clk1)
);
Wire Example
(* dont_touch = "true" *) wire sig1;
assign sig1 = in1 & in2;
assign out1 = sig1 & in2;
Module Example
(* DONT_TOUCH = "true|yes" *)
module example_dt_ver
(clk,
In1,
In2,
out1);
Instance Example
(* DONT_TOUCH = "true|yes" *) example_dt_ver U0
(.clk(clk),
.in1(a),
.in2(b),
out1(c));
VHDL Syntax
Declare the VHDL attribute as follows:
attribute DONT_TOUCH : string;
Specify the VHDL attribute as follows:
attribute DONT_TOUCH of name: label is "{TRUE|FALSE}";
Where
•name is the instance name of a user defined instance.
VHDL Syntax Example
attribute DONT_TOUCH : string;
-- Preserve the hierarchy of instance CLK1_rst_sync
attribute DONT_TOUCH of CLK1_rst_sync: label is "TRUE";
…
CLK1_rst_sync : reset_sync
PORT MAP (
RST_IN => RST_LOCKED,
CLK => clk1_100mhz,
RST_OUT => rst_clk1
);
XDC Syntax
set_property DONT_TOUCH {TRUE|FALSE} [get_cells <instance_name>]
set_property DONT_TOUCH {TRUE|FALSE} [get_nets <net_name>]
Where:
•instance_name is a leaf cell or hierarchical cell.
•net_name is the name of a hierarchical net.
XDC Syntax Example
# Preserve the hierarchy of instance CLK1_rst_sync
set_property DONT_TOUCH TRUE [get_cells CLK1_rst_sync]
# Preserve all segments of the hierarchical net named by the Tcl variables
set_property DONT_TOUCH [get_nets -segments $hier_net]
Affected Steps
•Synthesis
•Opt Design
•Phys Opt Design
•floorplanning
See Also