EQUALIZATION is available on differential receivers, implementing specific I/O standards, to overcome frequency-dependent attenuation through the transmission line.
Linear receiver equalization provides an AC gain at the receiver to compensate for high-frequency losses through the transmission line.
TIP: Equalization at the receiver can be combined with PRE_EMPHASIS at the transmitter to improve the overall signal integrity.
Architecture Support
UltraScale devices.
Applicable Objects
•Ports (get_ports)
Value
IMPORTANT: The EQUALIZATION values are not specifically calibrated. The recommendation is to run simulations to determine the best setting for the specific frequency and transmission line characteristics in the design. In some cases, lower equalization settings can provide better results than over-equalization. Over-equalization degrades the signal quality instead of improving it.
The allowed values for the EQUALIZATION attribute are:
•In HP I/O Banks
°EQ_LEVEL0
°EQ_LEVEL1
°EQ_LEVEL2
°EQ_LEVEL3
°EQ_LEVEL4
°EQ_NONE (default)
•In HR I/O Banks
°EQ_LEVEL0, EQ_LEVEL0_DC_BIAS
°EQ_LEVEL1, EQ_LEVEL1_DC_BIAS
°EQ_LEVEL2, EQ_LEVEL2_DC_BIAS
°EQ_LEVEL3, EQ_LEVEL3_DC_BIAS
°EQ_LEVEL4, EQ_LEVEL4_DC_BIAS
°EQ_NONE (default)
Syntax
Verilog and VHDL Syntax
Not applicable
XDC Syntax
The EQUALIZATION attribute uses the following syntax in the XDC file:
set_property EQUALIZATION value [get_ports port_name]
Where:
•set_property EQUALIZATION enables linear equalization at the input buffer.
•<Value> is one of the supported EQUALIZATION values for the specified port.
•port_name is an input or bidirectional port connected to a differential buffer.
See Also