IOB directs the Vivado tool to place a register that is connected to the specified port into the input or output logic block. Place this attribute on a port, connected to a register that you want to place into the I/O block.
IMPORTANT: With this property set to TRUE, the Vivado placer will only place the register into the IOB. The tool will not move the flop out of the IOB to improve timing since the IOB constraint takes precedence.
Architecture Support
All architectures.
Applicable Objects
•Ports (get_ports)
°Any port connected to a register
•Registers (get_cells)
Values
•TRUE: Place a connected register into the I/O Block.
•FALSE: Do not place the specified register into the I/O Block (default).
Syntax
Verilog Syntax
To set this attribute, place the proper Verilog attribute syntax before the top-level port declaration.
(* IOB = "{TRUE|FALSE}" *)
Verilog Syntax Example
// Place the register connected to ACK in the input logic site
(* IOB = "TRUE" *) input ACK,
VHDL Syntax
Declare and specify the VHDL attribute as follows:
attribute IOB : string;
attribute IOB of <port_name>: signal is "{TRUE|FALSE}";
Where:
•port_name is a top-level port.
VHDL Syntax Example
ACK : in std_logic;
attribute IOB : string;
-- Place the register connected to ACK in the input logic site
attribute IOB of ACK: signal is "TRUE";
XDC Syntax
set_property IOB value [get_ports port_name]
Where
•value is TRUE or FALSE.
XDC Syntax Example
# Place the register connected to ACK in the input logic site
set_property IOB TRUE [get_ports ACK]
Affected Steps
•Place Design
•Synthesis