The Input Output Block Delay (IOBDELAY) property specifies whether to add or remove delay in the ILOGIC block in order to help mitigate input hold times for system-synchronous data input capture.
The ILOGIC block is located next to the I/O block (IOB), and contains the synchronous elements for capturing data as it comes into the FPGA through the IOB. The ILOGIC block in 7 series FPGAs can be configured as ILOGICE2 in HP I/O banks, and as ILOGICE3 in HR I/O banks. ILOGICE2 and ILOGICE3 are functionally identical except that ILOGICE3 has a zero hold delay element (ZHOLD) which can be configured with IOBDELAY. Refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 2] or the UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 8] for more information on the use of IOBDELAY.
Architecture Support
All architectures.
Applicable Objects
•Ports (get_ports)
•Cells, for assignment to input buffers (IBUFs).
•Nets
Values
•NONE: Sets the delay to OFF for both the IBUF and input flip-flop (IFD) paths.
•IBUF
°Sets the delay to OFF for any register inside the I/O component.
°Sets the delay to ON for the buffered path through the ILOGIC block.
•IFD
°Sets the delay to ON for the IFF register inside the I/O component.
°Sets the delay to OFF for the BUFFERED path through the ILOGIC.
•BOTH: Sets the delay to ON for both the IBUF and IFD paths.
Syntax
Verilog Example
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* IOBDELAY = {NONE|BOTH|IBUF|IFD} *)
VHDL Example
Declare the VHDL constraint as follows:
attribute iobdelay: string;
Specify the VHDL constraint as follows:
attribute iobdelay of {component_name |label_name }: {component|label} is “{NONE|BOTH|IBUF|IFD}”;
XDC Syntax
set_property IOBDELAY value [get_cells cell_name]
Where:
•value is one of NONE, IBUF, IFD, BOTH
XDC Syntax Example
set_property IOBDELAY "BOTH" [get_nets {data0_I}]
Affected Steps
•Timing
•Placement
•Routing