IODELAY_GROUP groups IDELAYCTRL cells together with their associated IDELAY and ODELAY cells to allow proper placement and replication.
If you use IODELAY_GROUP to assign a group name to an IDELAYCTRL, you need to also associate an IDELAY or ODELAY cell to the group using the same IODELAY_GROUP property.
IMPORTANT: While an IODELAY_GROUP can contain multiple cells, a cell can only be assigned to one IODELAY_GROUP.
The following example uses set_property to group all the IDELAY/ODELAY elements associated with a specific IDELAYCTRL.
set_property IODELAY_GROUP IO_DLY1 [get_cells MY_IDELAYCTRL_inst]
set_property IODELAY_GROUP IO_DLY1 [get_cells MY_IDELAY_inst]
set_property IODELAY_GROUP IO_DLY1 [get_cells MY_ODELAY_inst]
Difference Between IODELAY_GROUP and HIODELAY_GROUP
IODELAY_GROUP can group elements across different hierarchies, whereas HIODELAY_GROUP names are made unique per hierarchy. Use IODELAY_GROUP to group I/O delay components from different hierarchies into a single group.
HIODELAY_GROUP groups I/O delay components under the same hierarchical module.
Architecture Support
All architectures.
Applicable Objects
•Cells (get_cells)
°IDELAY, ODELAY, or IDELAYCTRL instances
Values
Any specified group name
Syntax
Verilog Syntax
Place the Verilog attribute immediately before the instantiation of an IDELAY, ODELAY, or IDELAYCTRL.
(* IODELAY_GROUP = "value" *)
Verilog Syntax Example
// Specifies a group name of DDR_INTERFACE to an instantiated IDELAYCTRL
// IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
// Virtex-7
// Xilinx HDL Language Template, version 2014.1
// Specifies DDR_INTERFACE group name for IDELAYs/ODELAYs and IDELAYCTRL
(* IODELAY_GROUP = “DDR_INTERFACE” *)
IDELAYCTRL DDR_IDELAYCTRL_inst (
.RDY(), // 1-bit output: Ready output
.REFCLK(REFCLK), // 1-bit input: Reference clock input
.RST(1’b0) // 1-bit input: Active-High reset input
);
// End of DDR_IDELAYCTRL_inst instantiation
VHDL Syntax
Declare the VHDL attribute as follows:
attribute IODELAY_GROUP : string;
For an instantiated instance, specify the VHDL attribute as follows:
attribute IODELAY_GROUP of instance_name : label is "group_name";
Where
•instance_name is the instance name of an instantiated IDELAY, ODELAY, or IDELAYCTRL.
VHDL Syntax Example
// Specifies a group name of DDR_INTERFACE to an instantiated IDELAYCTRL
attribute IODELAY_GROUP : STRING;
attribute IODELAY_GROUP of DDR_IDELAYCTRL_inst: label is "DDR_INTERFACE";
begin
-- IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
-- Virtex-7
-- Xilinx HDL Language Template, version 2014.1
DDR_IDELAYCTRL_inst : IDELAYCTRL
port map (
RDY => open, -- 1-bit output: Ready output
REFCLK => REFCLK, -- 1-bit input: Reference clock input
RST => ‘0’ -- 1-bit input: Active-High reset input
);
-- End of DDR_IDELAYCTRL_inst instantiation
XDC Syntax
set_property IODELAY_GROUP group_name [get_cells instance_name]
Where
•group_name is a user-specified name for the IODELAY_GROUP.
•instance_name is the instance name of an IDELAY, ODELAY, or IDELAYCTRL.
XDC Syntax Example
# Specifies a group name of DDR_INTERFACE to an instantiated IDELAYCTRL
set_property IODELAY_GROUP DDR_INTERFACE [get_cells DDR_IDELAYCTRL_inst]
Affected Steps
•Placement
See Also
Refer to the following design elements in the Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953) [Ref 25] or the UltraScale Architecture Libraries Guide (UG974) [Ref 26].
°IDELAYCTRL
°IDELAYE2
°ODELAYE2