Versal Multi-Clock buffers (MBUFG) are clock buffers with multiple outputs that generate a /1, /2, /4, /8 version of the input clock on the output pins O1, O2, O3, O4 respectively. Clock buffers that are driven by the same clock modifying block such as MMCM, DPLL or XPLL or parallel clock buffers that have a common driver can be converted to an MBUFG clock primitive if the divide factors of the output clocks with relationship to the input clocks are 1, 2, 4, 8. The MBUFG_GROUP property can be applied to the clock nets driven by global clock buffers that have the same MMCM, PLL, GT, or a common driver that should be converted to an MBUFG primitive during the opt_design stage.
Architecture Support
Versal ACAP architectures.
Applicable Objects
Clock net segments (get_nets) directly connected to the output of global clock buffers (BUFG_PS, BUFGCE, BUFGCTRL, BUFGCE_DIV, BUFG_GT) that have a common driver and have clock period requirements related by a factor of 1, 2, 4, or 8.
Values
•<name>: A unique string identifier used by the Vivado placer to match the delays on specified clock nets.
Syntax
Verilog and VHDL Syntax
Not applicable
XDC Syntax
set_property MBUFG_GROUP <name> [get_nets <clk_nets>]
set_property MBUFG_GROUP <name> [get_nets -of_objects [get_pins <clock_buffer>/O]
Where
•<name> is the unique name to associate with the specified clock nets.
•<clk_nets> is a list of clock nets directly connected to the output of global clock buffers, that are driven by a common cell, such as an MMCM for example.
XDC Syntax Example
# Define a MBUFG group to convert parallel clock buffers to MBUFG.
set_property MBUFG_GROUP grp12 [get_nets {clk1_net clk2_net}]
Affected Steps
•Opt Design