The Post CRC Action property (POST_CRC_ACTION) applies to the configuration logic CRC error detection mode. This property determines the action that the device takes when a CRC mismatch is detected: correct the error, continue operation, or stop configuration. This feature is only supported in 7 series FPGAs. For more information refer to the 7 Series FPGAs Configuration User Guide (UG470) [Ref 1].
TIP: Alternatively, Xilinx recommends use of the Xilinx Soft Error Mitigation (SEM) IP for all architectures. This IP automates the implementation of single event upset (SEU) detection and correction. For additional information, refer to the Soft Error Mitigation Controller LogiCORE IP Product Guide (PG036) [Ref 28].
During readback, the syndrome bits are calculated for every frame. If a single bit error is detected, the readback is stopped immediately. If correction is enabled using the POST_CRC_ACTION property, then the readback CRC logic performs correction on single bit errors. The frame in error is readback again, and using the syndrome information, the bit in error is fixed and written back to the frame. If the POST_CRC_ACTION is set to Correct_And_Continue, then the readback logic starts over from the first address. If the Correct_And_Halt option is set, the readback logic stops after correction.
This property is only applicable when POST_CRC is set to ENABLE.
Architecture Support
7 series FPGAs.
Applicable Objects
•Design (current_design)
°The current implemented design.
Values
•HALT: If a CRC mismatch is detected, stop reading back the bitstream, stop computing the comparison CRC, and stop making the comparison against the pre-computed CRC.
•CONTINUE: If a CRC mismatch is detected by the CRC comparison, continue reading back the bitstream, computing the comparison CRC, and making the comparison against the pre-computed CRC.
•CORRECT_AND_CONTINUE: If a CRC mismatch is detected by the CRC comparison, it is corrected and continues reading back the bitstream, computing the comparison CRC, and making the comparison against the pre-computed CRC.
•CORRECT_AND_HALT: If a CRC mismatch is detected, it is corrected and stops reading back the bitstream, computing the comparison CRC, and making the comparison against the pre-computed CRC.
Syntax
Verilog and VHDL Syntax
Not applicable
XDC Syntax
set_property POST_CRC_ACTION <VALUE> [current_design]
Where:
•<VALUE> is one of the accepted values for the POST_CRC_ACTION property.
XDC Syntax Example
set_property POST_CRC_ACTION correct_and_continue [current_design]
Affected Steps
•Write Bitstream
•launch_runs
See Also