An SRL primitive can be converted to a logically equivalent chain of register primitives using the SRL_TO_REG property with a value of true. This transform is typically used to increase the number of available pipeline register stages that can be spread to allow signals to traverse long distances within a device.
Architecture Support
All architectures.
Applicable Objects
•Cells (get_cells) as leaf level shift register instances.
Value
•True (or 1): The Vivado logic optimization will convert the SRL chain into multiple register primitives.
•False (or 0): he Vivado logic optimization will not convert the SRL chain into multiple register primitives.
Syntax
Verilog and VHDL Syntax
Not applicable
XDC Syntax
set_property SRL_TO_REG <True | False> <objects>
The property is false by default. The objects should be static shift registers which can be instantiated or inferred, eg. SRL16E, SRL32E.
XDC Example:
set_property SRL_TO_REG 1 [get_cells {cell1 cell2}]
Affected Steps
•Opt Design
See Also