Stacked silicon interconnect (SSI) devices consist of multiple super logic regions (SLRs), joined by interposer connections called super long lines (SLLs). Paths crossing between SLRs through SLLs can present timing closure challenges.
Using SLL Laguna TX/RX registers can improve correlation between estimated and routed delays for nets that cross between SLR boundaries. Setting the USER_SLL_REG property on a register where the source cell of Reg/D and the load cell of Reg/Q are placed in different SLRs. Like the IOB property, the USER_SLL_REG property directs the Vivado placer to place the register into a nearby Laguna TX_REG or RX_REG site instead of the fabric if connectivity allows. For more information on placing and routing in and across SLRs, refer to this link in the UltraFast Design Methodology Guide for the Vivado Design Suite (UG949) [Ref 24].
TIP: The property is ignored when the nets do not cross an SLR boundary, or both the driver and the load are crossing the same SLR boundary, or the Red/Q net has loads in multiple SLRs.
For an FD cell with USER_SLL_REG property set to true, the placer will attempt to place the cell on a nearby LAGUNA site if the net connected to FD/D or FD/Q crosses an SLR boundary. The property will be ignored when:
•none of the nets connected to FD/D or FD/Q cross an SLR boundary,
•both nets connected to FD/D or FD/Q cross an SLR boundary,
•FD/Q net crosses an SLR boundary and has loads in 2 different SLRs.
For an FD cell with the USER_SLL_REG property set to false, the placer will never place the cell on a nearby LAGUNA site (hard constraint).
One technique to improve the placement of FD cells with the USER_SLL_REG property to a Laguna TX_REG or RX_REG, and decrease the algorithm runtime, is to constrain the FD cell to a clock region size PBLOCK that includes the LAGUNA sites.
IMPORTANT: This property is considered a guideline which the placer will attempt to follow, but can be overridden to achieve a valid placement result.
Architecture Support
UltraScale and UltraScale+ architectures.
Applicable Objects
•Cells (get_cells) as hierarchical modules or logical instances.
Value
•True (or 1): The Vivado placer will place (during detail placement) the FD cell on a LAGUNA site if the net connected to FD/D or FD/Q crosses an SLR boundary.
•False (or 0): Do not place the register into a LAGUNA site.
Syntax
Verilog and VHDL Syntax
Not applicable
XDC Syntax
set_property USER_SLL_REG <True | False> <objects>
XDC Example:
set_property USER_SLL_REG 1 [get_cells {cell1 cell2}]
The placer will try to place cell1 and cell2 into Laguna registers at the SLR boundary.
Affected Steps
•Placement
See Also