The IBERT PS-GTR Bring-up and subsequent EyeScan involves three different components:
- Generating Zynq UltraScale+ MPSoC PS Xilinx® Support Archive (XSA) file from the Vivado® tool after configuring the PS-GTR.
- Using the Vitis™ Xilinx Software Command-line Tool (XSCT) flow to generate a FSBL file using the XSA file.
- Using the FSBL file with Vivado Serial I/O Analyzer to bring up IBERT PS-GTR.
- XSCT (Part of the Vitis tool)
- ZCU102 Rev 1.0 board
- XCZU9EG-FFVB1156 production device
- A PCIe card which has at least x4 lanes
- PCI Express 4x Male to PCIe 16x Female Riser Cable if PCIe card is larger than x4
- SanDisk 128 GB SATA SSD Drive
- SATA connector cable
- 4 Pin Molex to SATA Power Cable Adapter
- SanDisk Ultra 32 GB USB 3.0 Flash Drive
- USB 3.0 Type A Female to Micro Male Adapter
- FSBL executable and linkable format file (ELF File) (Created using the following instructions) which configures the PS-GTR
- Configuration Bitstream File (Optional file that may be needed to custom configure the FPGA depending on the board setup)
- Tcl script to generate the FSBL and modify C-source for USB Support (when available)
- FSBL should always target Cortex®-A53 processor as R5 (psu_cortexr5_0) is exclusively used by IBERT PS-GTR.
- Physical devices such as SATA drive, PCIe card, etc. are needed for validation.