Step 1: Creating a New Vivado Project and Generating the IP Integrator Design with JTAG-to-AXI and System ILA - 2022.1 English

Vivado Design Suite Tutorial: Programming and Debugging (UG936)
Document ID
UG936
Release Date
2022-05-20
Version
2022.1 English
To create a project, use the New Project wizard to name the project, add RTL source files and constraints, and specify the target device.
  1. Invoke the Vivado® IDE.
  2. In the Quick Start tab, click Create Project to start the New Project wizard. Click Next.
  3. In the Project Name page, name the new project jtag_2_axi_tutorial and provide the project location (C:/jtag_2_axi_tutorial). Ensure that Create Project Subdirectory is selected. Click Next.
  4. In the Project Type page, specify the Type of Project to create as RTL Project. Ensure that Do not specify sources at this time is checked. Click Next.
  5. In the Default Part page, choose Boards and choose the Kintex-7 KC705 Evaluation Platform. Click Next.

  6. In the New Project Summary page, click Finish.

  7. In the leftmost panel of the Flow Navigator under Project Manager, click Create Block Diagram. A dialog box appears that allows you to specify a block diagram name. You can choose to specify a custom name or take the default. Click OK.

  8. In the far right of the window is an empty block diagram design window labeled Diagram. Click the + sign in the middle of the pane or the + toolbar button to bring up a search window. In the Search field, type “JTAG to AXI” and double-click it to add the JTAG to AXI Master to the block diagram.

  9. The JTAG to AXI Master core appears on the IP integrator canvas. Double-click the core to view the Customization dialog. Review the available settings and click OK to accept the default core settings.

  10. Following the same process from the previous step, add the additional IP to the block diagram: AXI BRAM controller and Block Memory Generator. This creates a design using a simple AXI infrastructure to create AXI transactions that demonstrate the debugging capabilities of the System ILA core.
  11. Before continuing, you need to customize AXI BRAM Controller and Block Memory Generator. Begin by locating the AXI BRAM Controller in the block diagram canvas and double-clicking on it. This invokes the Customization Dialog for the IP. Locate the Number of BRAM interfaces and set the value to 1. Click OK.

  12. Next, locate the Block Memory Generator in the block diagram and double-click as in the previous step to invoke the Customization dialog. Clear Enable Safety Circuit check box. Click OK.

  13. At this point the design should look like the following figure.

  14. Notice the green banner indicating that Designer Assistance is available at the top of the block diagram canvas. Click the Run Connection Automation button on this banner. When the Connection Automation window appears, click the radio button for All Automation, then click OK.

  15. Notice, that the Clocking Wizard and Processor System Reset as well as an AXI SmartConnect are auto-inserted into the design. Also, take note that the Clocking Wizard clock and reset inputs are not connected and the Run Connection Automation banner persists. These inputs will be connected to physical input ports on the FPGA, wired to buttons on the KC705 board though customization of the Clocking Wizard.
  16. Invoke the Customization Dialog for the Clocking Wizard by double-clicking the IP in the block diagram canvas. When the dialog appears, set CLKIN_1 to sys_diff_clk and EXT_RESET¬_IN to reset. Click OK.
    Note: It is not necessary to add constraints for these ports because the project has been generated using an evaluation board as the target and the IP allows the constraint information to be selected with the sys_diff_clk.


  17. Just as before, locate the green banner indicating that Designer Assistance is Available and click Run Connection Automation. When the Run Connection Automation dialog appears select the button for All Automation. Click OK.
  18. Now, sys_diff_clk and reset are connected to external ports. Examine the connectivity of the design and notice that it might be necessary to monitor AXI transactions between the JTAG to AXI master and the AXI BRAM Controller slave. This is possible if a System ILA is added to probe the AXI bus between the AXI BRAM Controller and the JTAG to AXI master.

  19. To add a System ILA to the design, click the Add IP (+) button as in previous steps. Search for System ILA, and double click to add it to the block diagram. When it appears in the block diagram canvas, double-click on it to invoke the Customization Dialog. Ensure that both Capture Control and Advanced Trigger are selected. Also, set the Number of Comparators to the value 3. Click OK.

  20. Now, make a connection between the System ILA SLOT_0_AXI port and the S_AXI port on the AXI BRAM Controller. Do this by clicking on the SLOT_0_AXI port and clicking again on the S_AXI port on the AXI BRAM Controller.

  21. When the Run Connection Automation banner appears, click it and select All Automation. Then click OK. Notice that the clk and resetn ports on the System ILA are connected to the AXI clock and the AXI reset.

  22. In the upper left side of the Vivado IDE, click File > Save Block Design. Select File > Close Block Design in the same menu to close the block design.
  23. In the sources window, right-click on design_1 block design and select Create HDL Wrapper. Allow Vivado IDE to manage the wrapper, and click OK.
  24. In the Flow Navigator on the left side of the Vivado IDE, click Generate Bitstream.
  25. Click OK to implement the design.
  26. Wait until the Vivado Status window shows write_bitstream complete.
  27. In the Bitstream Generation Completed dialog, select Open Hardware Manager, and click OK.