This simple tutorial shows you how to replace nets connected to an ILA core in a placed and routed design checkpoint using the Vivado® Design Suite Engineering Change Order (ECO) flow.
- Open the
Vivado® Design Suite, and select .
- Open the routed checkpoint that you created in Using the HDL Instantiation Method to Debug a Design.
Change the layout in the Vivado Design Suite toolbar drop-down to ECO.
Note: The Flow Navigator window now changes to ECO Navigator with a different set of options.
- In the ECO Navigator window, click Replace Debug
Probes to bring up the Replace Debug Probes dialog box. Note the
Debug Hub and ILA cores in the design.
Important: Xilinx strongly recommends that you do not replace the clock nets associated with ILA and Debug Hub cores.
- In the Replace Debug Probes dialog box, highlight the probes whose nets you want to change. In this lab you will replace the GPIO_BUTTONS_dly net that is being probed.
- Click the Edit Probes button to the
right of the GPIO_BUTTONS_dly probe net to bring up the Choose Nets dialog
- In the Choose Nets dialog box, choose the U_DEBOUNCE_0/clear net to replace
the existing GPIO_BUTTONS_dly probe net. Click OK.
- Type for “*clear net” in the Name field and Click Find. Notice the U_DEBOUNCE_0 net in the Found nets area. Select U_DEBOUNCE_0/clear net using the “->” arrow and click OK. The U_DEBOUNCE_0/clear net to replaces the existing
GPIO_BUTTONS_dly probe net.
- Now click OK in the Replace Debug
Probes dialog. An additional dialog box may appear if the nets were marked with
DONT_TOUCH indicating that it must be removed to proceed. If so, click Unset Property and Continue.
Important: Check the Tcl Console to ensure that there are no Warnings/Errors.