The following features are covered in the GTM-Wizard:
- Detection of designs with PAM4 signals, designs instantiating GTM_DUAL and automatic
generation bypass module (
xil_dut_bypass
). - Simple sanity check for design that should instantiate bypass module.
- A mechanism to view PAM4 signals in Waveform Viewer for XSim users.
- Provide a way to generate bypass module for export simulation flow.
In this tutorial, we would generate an GTM-Wizard example design, which usage PAM4 signal. To generate that, please follow steps below:
- Create project in Vivado 2022.1 without adding source/constraint file .
- In
the Default Part page,
select Virtex UltraScale+ 58G and select
parts as shown in the following figure and click Next.
- Check the summary report and click Finish.
- Under Project
Manager, click on IP
Catalog and search for
gtm_wizard
and then double-click Virtex UltraScale+ FPGAs Transceivers Wizard.
- Click OK on default
configuration and click Skip on
Generate Output
Product dialog box.
- On Sources window, right-click the generated XCI file,
click Open IP Example Design, and specify
the location.
At this stage, you have an example ready to run simulation.
Before heading towards simulation, here are few things from PAM4 point of view:
-
xil_dut_bypass
module definition is generated on run time by tool which contain hierarchical reference to GTM_DUAL.
- This
xil_dut_bypass
module generation is controled by the Configure Design for Hierarchical Access option, which is set by default.
Note: For old behavior, please uncheck Configure Design for Hierarchical Access.Once design is created, we can run it either through
launch_simulation
orexport_simulation
.
- Launch_simulation
-
- Click Run Behavioral Simulation.
This will run simulation with Vivado Simulator.
- Once snapshot is created and loaded, simulation will stop after 1000 ns.
Let’s look at xil_dut_bypass definition. Double-click xil_dut_bypass in the
Scope
window to see the source file. Notice the hierarchical reference
from the top module till the leaf level instance.
- Right-click xil_dut_bypass and add
to waveform.
- Click Restart then run all.
- Once simulation is complete, section all signal of xil_dut_bypass in
waveform, right-click and select Waveform
Style to Analog.
- Go to analog setting under waveform style and change the value like below
for better waveform.
- Observe the analog value of signals.
Note: For running same design with third party simulators, please refer to Vivado Design Suite User Guide: Logic Simulation (UG900)
- Click Run Behavioral Simulation.
This will run simulation with Vivado Simulator.
- Export_simulation
- The following are the two flows for export simulation:
- Export simulation with xil_dut_bypass generated
-
- Invoke command
export_simulation -simulator xsim -generate_hier_access
on Vivado IDE.This generates scripts in <your_local_path>/export_sim/xsim.
- In the generated vlog.prj, observe
xil_dut_bypass.sv
. This is because launch_simulation has generated and added this as part of project.
- Invoke
gtm_wizard_ultrascale_0_example_top_sim.sh
it runs the simulation. If you want to run in GUI mode, add-gui
to xsim command of else part. - Follow step-3 to step-7 under launch_simulation and you will able to see same waveform/output as launch_simulation.
- Invoke command
- Export simulation without xil_dut_bypass
-
- Invoke
gtm_wizard_ultrascale_0_example_top_sim.sh -gen_bypass
. - It runs the simulation for delta time unit and generate hierarchical path in log file.
- In generated simulate.log, note down the entry
xilinx_hier_bypass_ports:gtm_wizard_ultrascale_0_example_top_sim.u_e….
- Generate
xil_dut_bypass.sv
by invokinggenerate_hier_access -log ./simulate.log
on Vivado TCL console. - Observe
xil_dut_bypass.sv
generate in current directory. - Add this
xil_dut_bypass.sv
in vlog.prj assv xil_defaultlib ./xil_dut_bypass.sv
. - Invoke
gtm_wizard_ultrascale_0_example_top_sim.sh
it runs simulation. If you want to run in GUI mode, add-gui
to xsim command of else part.
- Follow step-3 to step-7 under launch_simulation and you can see same waveform/output as launch_simulation.
- Invoke
- Generating xil_dut_bypass for non-vivado project
-
- Create compile order of the design (<design>.prj).
- Execute XSim simulator tools to generate the simulator log file:
-
xelab -prj <design>.prj -top <testbench-top>
. -
xsim -R <testbench-top> --testplusarg GEN_BYPASS
.
-
- Verify
<simulator>.log
file generated and that it contains thexilinx_hier_bypass_ports
string with the hierarchical path information. For example:xilinx_hier_bypass_ports:tb.dut_i.gtmWiz_00.gtm_i in:integer:in1:in_var1 in:integer:in2:in_var2 out:integer:out1:out_var1 out:integer:out2:out_var2
- Download
generate_hier_access.tcl
utility from GitHub:wget https://raw.githubusercontent.com/Xilinx/XilinxTclStore/2020.1-dev/tclapp/xilinx/projutils/generate_hier_access.tcl
- Execute
generate_hier_access.tcl
to generate the sources for hierarchical access simulation:-
# /usr/bin/tclsh
. -
source generate_hier_access.tcl
. -
generate_hier_access -bypass dut_bypass -testbench <module> -directory <path> -log <simulator>.log
. Instantiate thisdut_bypass
in test bench with proper connection.
-
- Add
<path>/dut_bypass.sv
to <design>.prj. - Run simulator tools to simulate the design in <design>.prj.