Xilinx IP in the IP catalog are delivered as RTL source. This provides the benefit of being able to perform behavioral simulation, which is faster than netlist-based simulation. However, synthesizing each IP along with the overall design, with every design iteration, can add significant synthesis time to the project development.
The design checkpoint (DCP) file delivered with the IP core output products, and generated by the out-of-context (OOC) synthesis run, eliminates the need to re-synthesize the core over multiple iterations.
The default behavior of the Vivado Design Suite is to generate the necessary output products, including the DCP file, when you create an IP customization.
You can disable generation of the DCP file, as well as defer generating output products until later.
- In the Hierarchy tab of the Sources window, look at the
clk_core IP customization instantiated under the
top-level of the design, wave_gen/clk_gen_i0.
Notice that the clk_core IP cannot be expanded with the ‘>’ icon like you can expand the char_fifo IP. This indicates that no output products exist for the clk_core when it was instanced in the project.
- In the Sources window > IP Sources view, click the Plus (>) icon next to the char_fifo IP.
The Vivado tool displays the Show IP Hierarchy dialog box, (following figure), warning you that expanding the hierarchy of very large IP cores can add significant delay to updating the hierarchy in the Sources window.
Note: If you do not get the same results, ensure that you are in the Source Window > IP Sources view.
- Click Cancel to close the Show IP Hierarchy dialog
If you skip generation of output products when the IP is customized, the Vivado® Design Suite automatically generates the required output products at the point in the design flow they become necessary, such as during synthesis or simulation.
By default, a DCP file for an IP core is created unless you disable this in the Generate Output Products dialog box. See the Vivado Design Suite User Guide: Designing with IP (UG896) for more information. If DCP file generation is disabled, the IP RTL synthesizes along with the top-level design.
- In the Flow Navigator, click the Run
The Vivado tool automatically creates a new OOC module synthesis run for the clk_core, and launches that synthesis run as seen in the following figure.
This synthesis run creates the DCP file for the IP customization.
- When the
clk_coresynthesis run is finished, click OK.
You can examine the contents of the IP Sources tab of the Sources window. You will see the output products generated by the Vivado tools for the IP, (following figure).
With the required output products for the clk_core created, the Vivado synthesis tool runs on the top-level of the design, (see the following figure).
When the top-level of the design is synthesizing, Vivado synthesis infers a black box for the FIFO generator IP (char_fifo) and the Clock generator IP (clk_core) in the design.
- When the Synthesis Completed dialog box opens, select the View
Reports option, and click OK.
This opens the Reports window at the bottom of the Vivado IDE.
- Switch to the Reports window, and select .
- In the Log window, click the Find button to search for “blackbox.”
- Click Find Next until you come to the
following section, which summarizes the black boxes found in the current design,
then click Next. The following figure is
a snippet of the "Report BlackBoxes" report.
- Review the report.
You can also review the project IP runs folder for the results of the out-of-context synthesis runs:
You can use the IP customizations created in other projects by adding the XCI file as a source. All the output products for the IP, including the DCP, are used automatically. If you change the part, you must update the IP and regenerate the output products.