- If open, close the Manage IP project or launch Vivado.
- From the Getting Started page of Vivado, select Create Project and then select Next.
- In the Project Name dialog box, provide a project name and specify a location:
- Project name
- Project location
- Leave the Create project subdirectory checked, and click Next.
- Set the Project type to be a
Post-synthesisproject and leave the Do not specify sources at this time box unchecked.
- In the Add Netlist Sources window, browse for and select the following files:
- <extract_dir>/lab_2/sources, and select wave_gen.edf
- <extract_dir>/lab_2/my_ip/char_fifo (or wherever you put the Manage IP project) and select char_fifo.xci
<extract_dir>/lab_2/my_ip/clk_core and select
You can either remotely reference the source files or copy them into the netlist project.
- Ensure that the wave_gen.edf is set as
top, as shown in the following figure, then click Next to continue.
- In the Add Constraints window, browse to the
<Extract_Dir>/lab_2/sources area and select the
- Again, either reference them remotely or add them to your project.
- Click Next when done selecting the two files.
- In the Default Part window, select the xc7k70tfbg676-1 and click Next.
The New Project Summary window opens, as shown in the following figure.
- Click Finish.
The newly created netlist project opens.
- Expand the sources window as shown in the following figure, to see the
netlist, IP, and constraints that comprise the project.
In a netlist project you can check the status of the IP that are present.
Even if the IP is no longer current, because you have all the output products, you can proceed through implementation.
, and see that the IP are locked. This is because changing IP in a
netlist design requires you to modify them from their original project or a
Managed IP project.
- Select the Compile Order tab and
select Implementation to see the order in
which the design source files and constraints are processed (see the following
- In the Tcl Console, type:
report_compile_orderYou see three sections:
- Source compile order for implementation
- Lists the EDIF and DCP sources that are used during implementation. The only thing used from the DCPs for the IP are the EDIF netlists.
- Source compile order for simulation
- RTL sources for the IP set to be used during implementation. There are no top-level simulation files for this project so simulation cannot be performed at this time on the project.
- Constraint evaluation order for implementation
- IP XDC output product files as well as the two top-level constraint files. The constraints in the IP DCP files are not used.
The Launch Runs dialog box appears.
- Click OK.
- After implementation completes, select Report Timing
Summary in the Flow Navigator to open the implemented design and
report timing. View and familiarize yourself with the feature.Important: The design does not meet Timing at this point of the flow.
You could also script this flow.
See the .jou file for the script commands for a project flow. Continue to the next section for information on how to create a non-project based flow script.
The process to implement the design consists of bringing the netlist from the third-party synthesis tool into Vivado® , the two IP customizations created in the Manage IP project, and top-level constraints. The EDIF netlist and the top-level XDC files are provided for you.