Step 7: Run Implementation - 2022.1 English

Vivado Design Suite Tutorial: Designing with IP (UG939)

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2022.1 English
With synthesis completed, you are now ready to script implementation. There are many steps to implementation, in both Project Mode and Non-Project Mode. However, in Project Mode, you select a design run strategy that controls all of the various steps, and launch that run. In Non- Project Mode, without a design run, you must determine your implementation strategy by manually running each step of implementation, and selecting the Tcl command options to use at each step. You can also choose to skip some steps, such as logic optimization, power optimization, and physical synthesis.

In this lab, you run the following steps:

  • Logic optimization: opt_design
  • Placement: place_design
  • Physical synthesis: phys_opt_design
  • Routing: route_design
  • Bitstream generation: write_bitstream

For a complete description of each of these steps, see Vivado Design Suite User Guide: Implementation (UG904).

Between each of these steps, you can generate reports, and write checkpoints to save the design in different stages of implementation.

Before launching implementation, you must read the design constraints that are only used in implementation. The XDC file, top_physical.xdc, contains physical constraints that are used in implementation, but do not apply to synthesis.

In this case, these constraints could have been read into the in-memory design prior to synthesis, because synthesis ignores them; however, this file could also contain different timing constraints, not to be used in synthesis, that must be read in after synthesis and just prior to implementation.

  1. Add the following line to your Tcl script:
    read_xdc ../Lab_3_4_sources/Constraints/top_physical.xdc
  2. Add optimization and placement commands to your Tcl script:
    write_checkpoint -force post_place.dcp
    report_timing -file timing_place.rpt

    After placement completes, your script writes a post-placement checkpoint and create a custom timing report, which provides a detailed timing report for the single worst timing path in the design.

  3. Add physical synthesis and routing commands to your Tcl script:
    write_checkpoint -force post_route.dcp
    report_timing_summary -file timing_summary

    After routing completes, your script writes a post-routing design checkpoint and creates a timing summary report.

  4. Finally, write out a bitstream by adding the following:
    write_bitstream -force sys_integration_top.bit

This is the complete Non-Project Mode design flow for implementing a design from RTL source files, including designing with IP, through bitstream generation.