Adding Timing Exceptions between Asynchronous Clocks - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

Timing paths in which the source and destination clocks originate from different primary clocks or have no common node, no common phase, or no common period must be treated as asynchronous clocks. In this case, the skew can be extremely large, making it impossible to close timing.

You must review all timing paths between asynchronous clocks to ensure the following:

  • Proper asynchronous clock domain crossing circuitry (report_cdc)
  • Timing exception definitions that ignore timing analysis (set_clock_groups, set_false_path) or ignore skew (set_max_delay -datapath_only)

You can use the Clock Interaction Report (report_clock_interaction) to help identify clocks that are asynchronous and are missing proper timing exceptions.

Figure 1. Asynchronous CDC Paths with Proper CDC Circuitry and No Common Node