Report QoR Assessment combines logic level checks, utilization checks, and the most common clocking topology checks into one summary report that gives you an overall assessment of the design. This report helps you understand the severity of the timing closure issues. Xilinx recommends that you run this report on the synthesized design after any significant netlist update on a design with correct timing constraints.
Report QoR Assessment provides a score between 1 and 5 that indicates how likely the design is to close timing. The following table shows the definition of each score. Scores of 1 and 2 have no chance of meeting timing closure and a score of 3 is unlikely to close. Therefore, low scores mean more work in closing timing.
|1||Design will likely not complete implementation.|
|2||Design will complete implementation but will not meet timing.|
|3||Design will likely not meet timing.|
|4||Design will likely meet timing.|
|5||Design will meet timing.|
In the report, the detailed table provides information on the basis for the score. The thresholds in the detailed table are not absolute limits for the device. Instead, the thresholds indicate when timing closure might become increasingly difficult to achieve. After you exceed the threshold of any of these items, the difficulty in closing timing increases exponentially.
Plan to correct any items that are marked for review in the Report QoR assessment. Many of the items might be resolved automatically using Report QoR Suggestions.