Balance Pipeline Depth and SRL Usage - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

When there are deep register pipelines, map as many registers as possible into the SRLs to avoid significant increases in register utilization. For example, a 9-deep pipeline for a data width of 32 results in 9 registers for each bit, which uses 32 x 9 = 288 registers. Mapping the same structure to SRLs uses 32 SRLs. Each SRL has address pins A4 through A0 connected to 5'b01000 to implement a depth of 9 stages.

There are multiple ways to infer SRLs during synthesis, including the following:

  • SRL
  • REG -> SRL
  • SRL -> REG
  • REG -> SRL -> REG

You can create these structures using the srl_style attribute in the RTL code as follows:

  • (* srl_style = "srl" *)
  • (* srl_style = "reg_srl" *)
  • (* srl_style = "srl_reg" *)
  • (* srl_style = "reg_srl_reg" *)

A common mistake is to use different enable/reset control signals in deeper pipeline stages. Following is an example of a reset used in a 9-deep pipeline stage with the reset connected to the third, fifth, and eighth pipeline stages. With this structure, the tools map the pipeline stages to registers only, because there is a reset pin on the SRL primitive.

FF->FF->FF(reset) -> FF->FF(reset)->FF->FF->FF(reset)->FF

To take advantage of SRL inference:

  • Ensure there are no resets for the pipeline stages.
  • Analyze whether the reset is really required.
  • Use the reset on one flip-flop (for example, on the first or last stage of the pipeline).