Block Design Synthesis - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

The block design synthesis flow allows you to create complex systems using custom and Xilinx IP. In this flow, a block design (BD) file is created using the Vivado IP integrator. Xilinx or custom IP is added to the .bd file and connected as a system. This flow offers the following advantages:

  • Encapsulates a great deal of functionality into a small design.
  • Allows focus on the system rather than individual parts of the system.
  • Enables easier and faster setup and synthesis of the design.

The following figure shows an example of a block design.

Figure 1. Block Design Example

When creating the block design, you can run synthesis using either out-of-context (OOC) synthesis mode or global synthesis mode. If you use out-of-context synthesis mode, the block design is synthesized separately from the rest of the design. This allows for faster resynthesis when hierarchies outside the BD file are modified. If you use global synthesis mode, the full design is compiled and synthesized each time. Global synthesis mode is easier to set up because constraints are set on a global level. However, using this mode results in a higher run time on resynthesis. You can improve run time using incremental synthesis.