Most clocks enter the device through a global clock-capable I/O (GCIO) pin. These clocks directly drive the clock network via a clock buffer or are transformed by a PLL or MMCM located in the clock management tile (CMT) adjacent to the I/O column.
The CMT contains the following clocking resources:
- Clock generation blocks
- 2 PLLs
- 1 MMCM
- Global clock buffers
- 24 BUFGCEs
- 8 BUFGCTRLs
- 4 BUFGCE_DIVs
The GT user clocks drive the global clock network via BUFG_GT buffers. There are 24 BUFG_GT buffers per clock region adjacent to the GTH/GTY columns.
Following is summary information for each of the UltraScale device clock buffers:
The most commonly used buffer is the BUFGCE. This is a general clock buffer with a clock enable/disable feature equivalent to the 7 series BUFHCE.
The BUFGCE_DIV is useful when a simple division of the clock is required. It is considered easier to use and more power efficient than using an MMCM or PLL for simple clock division. When used properly, it can also show less skew between clock domains as compared to an MMCM or PLL when crossing clock domains. The BUFGCE_DIV is often used as replacement for the BUFR function in 7 series devices. However, because the BUFGCE_DIV can drive the global clock network, it is considered more capable than the BUFR component.
- BUFGCTRL (also BUFGMUX)
The BUFGCTRL can be instantiated as a BUFGMUX and is generally used when multiplexing two or more clock sources to a single clock network. As with the BUFGCE and BUFGCE_DIV, it can drive the clock network for either regional or global clocking.
When using clocks generated by GTs, the BUFG_GT clock buffer allows connectivity to the global clock network. In most cases, the BUFG_GT is used as a regional buffer with its loads placed in one or two adjacent clock regions. The BUFG_GT has built-in dynamic clock division capability that you can use in place of an MMCM for clock rate changes.
You can use the Clock Utilization Report in the Vivado IDE to visually analyze clocking resource utilization and clock routing. The following figure shows the clock resource utilization per clock region overlaid in the Device window. For more information on this report, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
For more information on the BUFGCE, BUFGCE_DIV, and BUFGCTRL buffers, see the UltraScale Architecture Clocking Resources User Guide (UG572). For details on connectivity and use of the BUFG_GT buffer, see the appropriate UltraScale Architecture Transceiver User Guide: