Xilinx devices use various types of routing resources to support most common clocking schemes and requirements such as high fanout clocks, short propagation delays, and extremely low skew. Clock skew affects any register-to-register path with either a combinational logic or interconnect between them.
report_design_analysis) to generate a timing report, which includes
information on clock skew data. Verify that the clock nets do not contain excessive
Clock skew in high performance clock domains (+300 MHz) can impact performance. In
general, the clock skew should be no more than 500 ps. For example, 500 ps represents
15% of a 300 MHz clock period, which is equivalent to the timing budget of 1 or 2 logic
levels. In cross domain clock paths the skew can be higher, because the clocks use
different resources and the common node is located further up the clock trees. SDC-based
tools time all clocks together unless constraints specify that they should not be (for
If the clock uncertainty is over 100 ps, then you must review the clock topology and jitter numbers to understand why the uncertainty is so high.